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cy7c056v cy7c057v 3.3 v 16k/32k x 36 flex36? asynchronous dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06055 rev. *f revised october 14, 2011 features true dual-ported memory cells that allow simultaneous access of the same memory location 16k x 36 organization (cy7c056v) 32k x 36 organization (cy7c057v) 0.25-micron complimentary metal oxide semiconductor (cmos) for optimum speed/power high-speed access: 12/15 ns low operating power ? active: i cc = 250 ma (typical) ? standby: i sb3 = 10 ? a (typical) fully asynchronous operation automatic power-down expandable data bus to 72 bits or more using master/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to- port communication byte select on left port bus matching on right port depth expansion via dual chip enables pin select for master or slave commercial and industrial temperature ranges available in 144-pin thin quad plastic flatpack (tqfp) or 172-ball ball grid array (bga) pb-free packages available compact packages: ? 144-pin tqfp (20 x 20 x 1.4 mm) ? 172-ball bga (1.0-mm pitch) (15 x 15 x.51 mm) notes 1. a 0 ?a 13 for 16k; a 0 ?a 14 for 32k devices. 2. busy is an output in master mode and an input in slave mode. r/w l ce 0l ce 1l oe l i/o control address decode busy l ce l interrupt semaphore arbitration sem l int l m/s r/w r ce 0r ce 1r oe r ce r logic block diagram a 0l ?a 13/14l true dual-ported ram array busy r sem r int r address decode a 0r ?a 13/14r [2] [2] [1] [1] 14/15 14/15 14/15 14/15 left port control logic i/o 18l ?i/o 26l 9 i/o 27l ?i/o 35l 9 i/o 0l ?i/o 8l 9 i/o 9l ?i/o 17l 9 right port control logic i/o control 9 9 i/o r 9 9 bus match 9/18/36 ba bm size wa b 0 ?b 3 cy7c056v cy7c057v cy7c037v cy7c038v3.3 v 16k/32k x 36 flex36? asynchronous dual-port static ram
cy7c056v cy7c057v document #: 38-06055 rev. *f page 2 of 27 contents functional description ..................................................... 3 pin configurations ........................................................... 4 pin configurations (continued) ....................................... 5 selection guide ................................................................ 5 pin definitions .................................................................. 6 maximum ratings[6] ........................................................ 7 operating range ............................................................... 7 electrical characteristics over the operating range[8]........................................... 8 capacitance[10] ................................................................ 8 ac test load and waveforms ......................................... 9 switching characteristics over the operating range[13] ....................................... 10 data retention mode ...................................................... 11 timing .............................................................................. 11 read cycle no. 1 (either port address access) ........ 12 read cycle no. 2 (either port ce /oe access) ........... 12 read cycle no. 3 (either port) .......................................... 12 switching waveforms .................................................... 12 write cycle no. 1: r/w controlled timing ................. 13 write cycle no. 2: ce controlled timing ................... 13 semaphore read after write timing, either side ...... 14 timing diagram of semaphore contention ................ 14 timing diagram of write with busy (m/s = high).... 15 write timing with busy input (m/s = low) ............... 15 busy timing diagram no. 1 (ce arbitration).............. 16 busy timing diagram no. 2 (address arbitration) ..... 16 architecture .................................................................... 18 functional description ............ .............. .............. ........... 18 write operation ......................................................... 18 read operation ....... .............. .............. .............. ........ 18 interrupts ................................................................... 18 busy .......................................................................... 18 master/slave ............................................................. 18 semaphore operation ............................................... 18 right port configuration ................................................. 20 right port operation ...................................................... 20 left port operation ......................................................... 20 bus match operation ..................................................... 20 long-word (36-bit) operation ................................... 21 word (18-bit) operation ............................................. 21 byte (9-bit) operation ................................................ 21 ordering information ...................................................... 22 ordering code definition .... ....................................... 22 package diagrams .......................................................... 23 acronyms ........................................................................ 25 document conventions ................................................. 25 units of measure ....................................................... 25 sales, solutions, and legal information ...................... 27 worldwide sales and design s upport ......... .............. 27 products .................................................................... 27 psoc solutions ......................................................... 27
cy7c056v cy7c057v document #: 38-06055 rev. *f page 3 of 27 functional description the cy7c056v and cy7c057v are low-power cmos 16k and 32k x 36 dual-port static rams. various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be utilized as standalone 36-bit dual-port static rams or multiple devices can be combined in order to function as a 72-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 72-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multiprocessor des igns, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ) [3] , read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphor e) at any time. control of a semaphore indicates that a sh ared resource is in use. an automatic power-down feature is controlled independently on each port by chip select (ce 0 and ce 1 ) pins. the cy7c056v and cy7c057v are available in 144-pin thin quad plastic flatpack (tqfp) and 172-ball ball grid array (bga) packages. note 3. ce is low when ce 0 ? v il and ce 1 ?? v ih .
cy7c056v cy7c057v document #: 38-06055 rev. *f page 4 of 27 pin configurations notes 4. this pin is a14l for cy7c057v. 5. this pin is a14r for cy7c057v i/o32l i/o33r i/o23l i/o33l 2 3 4 i/o34l i/o34r 5 i/o35l i/o35r 6 a0l a0r 7 a1l a1r 8 a2l a2r 9 a3l a3r 10 a4l a4r 11 a5l a5r 12 a6l a6r 13 a7l 108 a7r 14 b0 107 bm 15 b1 106 size 16 b2 105 wa 17 b3 104 ba 18 oel 103 oer 19 r/wl 102 r/wr 20 vdd 101 vdd 21 vss 100 vss 22 vss 99 vdd 23 ce0l 98 ce0r 24 ce1l 97 ce1r 25 m/s 96 vdd 26 seml 95 semr 27 intl 94 intr 28 busyl 93 busyr 29 a8l 92 a8r 30 a9l 91 a9r 31 a10l 90 a10r 32 a11l 89 a11r 33 a12l 88 a12r 34 a13l 87 a13r 35 nc 86 nc 36 i/o26l 85 i/o26r i/o25l 84 i/o25r i/o24l 83 i/o24r 82 81 41 42 43 44 i/o22l i/o31l 45 vss vss 46 i/o21l i/o30l 47 i/o20l i/o29l 48 i/o19l i/o28l 49 i/o18l i/o27l 50 vdd vdd 51 i/o8l i/o17l 52 i/o7l i/o16l 53 i/o6l i/o15l 54 i/o5l i/o14l 55 vss vss 56 i/o4l i/o13l 57 i/o3l i/o12l 58 i/o2l 143 i/o11l 59 i/o1l 142 i/o10l 60 i/o0l 141 i/o9l 61 i/o0r 140 i/o9r 62 i/o1r 139 i/o10r 63 i/o2r 138 i/o11r 64 i/o3r 137 i/o12r 65 i/o4r 136 i/o13r 66 vss 135 vss 67 i/o5r 134 i/o14r 68 i/o6r 133 i/o15r 69 i/o7r 132 i/o16r 70 i/o8r 131 i/o17r 71 vdd 130 vdd 72 i/o18r 129 i/o27r 123 i/o19r 128 i/o28r 122 i/o20r 127 i/o29r 121 i/o21r 126 i/o30r 120 vss 125 vss 119 i/o22r 124 i/o31r 118 i/o23r i/o32r 117 116 37 38 39 40 80 79 78 77 76 75 74 73 115 114 113 112 111 110 109 144 1 cy7c056v (16k x 36) cy7c057v (32k x 36) [4] [5] figure 1. 144-pin thin quad flatpack (tqfp) top view
cy7c056v cy7c057v document #: 38-06055 rev. *f page 5 of 27 pin configurations (continued) figure 2. 172-ball ball grid array (bga) top view 1 2 3 4 567891011121314 a i/o32l i/o30l nc vss i/o13l vdd i/o11l i/o11r vdd i/o13r vss nc i/o30r i/o32r b a0l i/o33l i/o29 i/o17l i/o14l i/o12l i/o9l i/o9r i/o12r i/o14r i/o17r i/o29r i/o33r a0r c nc a1l i/o31l i/o27l nc i/o15l i/o10l i/o10r i/o15r nc i/o27r i/o31r a1r nc d a2l a3l i/o35l i/o34l i/o28l i/o16l vss vss i/o16r i/o28r i/o34r i/o35r a3r a2r e a4l a5l nc b0l nc nc nc nc bm nc a5r a4r f vdd a6l a7l b1l nc nc size a7r a6r vdd g oel b2l b3l ce0l ce0r ba wa oer h vss r/w la8lce1l ce1r a8r r/w rvss j a9l a10l vss m/s nc nc vdd vdd a10r a9r k a11l a12l nc seml nc nc nc nc semr nc a12r a11r l busyl a13l intl i/o26l i/o25l i/o19l vss vss i/o19r i/o25r i/o26r intr a13r busyr m nc nc [4] i/o22l i/o18l nc i/o7l i/o2l i/o2r i/o7r nc i/o18r i/o22r nc [5] nc n i/o24l i/o20l i/o8l i/o6l i/o5l i/o3l i/o0l i/o0r i/o3r i/o5r i/o6r i/o8r i/o20r i/o24r p i/o23l i/o21l nc vss i/o4l vdd i/o1l i/o1r vdd i/o4r vss nc i/o21r i/o23r selection guide cy7c056v cy7c057v -12 cy7c056v cy7c057v -15 unit maximum access time 12 15 ns typical operating current 250 240 ma typical standby current for i sb1 (both ports ttl level) 55 50 ma typical standby current for i sb3 (both ports cmos level) 10 ? a 10 ? a ? a
cy7c056v cy7c057v document #: 38-06055 rev. *f page 6 of 27 pin definitions left port right port description a 0l ?a 13/14l a 0r ?a 13/14r address (a 0 ?a 13 for 16k; a 0 ?a 14 for 32k devices) sem l sem r semaphore enable ce 0l , ce 1l ce 0r , ce 1r chip enable (ce is low when ce 0 ? v il and ce 1 ?? v ih ) int l int r interrupt flag busy l busy r busy flag i/o 0l ?i/o 35l i/o 0r ?i/o 35r data bus input/output oe l oe r output enable r/w l r/w r read/write enable b 0 ?b 3 byte select inputs. asserting these si gnals enables read and write operations to the corresponding bytes of the memory array. bm, size see bus matching for details. wa, ba see bus matching for details. m/s master or slave select v ss ground v dd power
cy7c056v cy7c057v document #: 38-06055 rev. *f page 7 of 27 maximum ratings [6] exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ................................ ?65 ? c to +150 ? c ambient temperature with power applied ........................................... ?55 ?? c to +125 ? c supply voltage to ground potenti al ...............?0.5 v to +4.6 v dc voltage applied to outputs in high z state........................... ?0.5 v to v dd +0.5 v dc input voltage .................................?0.5 v to v dd +0.5 v [7] output current into outputs (low) .............................. 20 ma static discharge voltage........................................... >2001 v latch-up current ..................................................... >200 ma notes 6. the voltage on any input or i/o pin can not exceed the power pin during power-up 7. pulse width < 20ns operating range range ambient temperature v dd commercial 0 ? c to +70 ? c 3.3 v 165 mv industrial ?40 ? c to +85 ? c 3.3 v 165 mv
cy7c056v cy7c057v document #: 38-06055 rev. *f page 8 of 27 notes 8. deselection for a port occurs if ce 0 is high or if ce 1 is low. 9. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . 10. tested initially and after any design or process changes that may affect these parameters. electrical characteristics over the operating range [8] parameter description cy7c056v cy7c057v unit -12 -15 min typ max min typ max v oh output high voltage (v dd = min., i oh = ?4.0 ma) 2.4 ? 2.4 ? ?v v ol output low voltage (v dd = min., i ol = +4.0 ma) ?0.4? 0.4v v ih input high voltage 2.0 ? 2.0 ? v v il input low voltage ? 0.8 ? 0.8 v i oz output leakage current ?10 10 ?10 10 ? a i cc operating current (v dd = max., i out = 0 ma) output disabled commercial ? 250 385 ? 240 360 ma industrial ? 265 385 ma i sb1 standby current (both ports ttl level and deselected) f = f max commercial 55 75 50 70 ma industrial ?6595ma i sb2 standby current (one port ttl level and deselected) f = f max commercial 180 240 175 230 ma industrial ? 190 255 ma i sb3 standby current (both ports cmos level and deselected) f =0 commercial 0.01 1 0.01 1 ma industrial ? 0.01 1 ma i sb4 standby current (o ne port cmos level and deselected) f = f max [9] commercial 160 210 155 200 ma industrial ? 170 215 ma capacitance [10] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v 10 pf c out output capacitance 10 pf
cy7c056v cy7c057v document #: 38-06055 rev. *f page 9 of 27 notes 11. external ac test load capacitance = 10 pf. 12. (internal i/o pad capacitance = 10 pf) + ac test load. ac test load and waveforms v th = 1.5 v output c (a) normal load (load 1) r = 50 ? z 0 = 50 ? [11] 3.0 v v ss 90% 90% 10% 3ns 3 ns 10% ? ? all input pulses 3.3 v output c = 5 pf (b) three-state delay (load 2) r2 = 435 ? r1 = 590 ? 1 2 3 4 5 6 7 30 60 80 100 200 ?? for access time (ns) capacitance (pf) 20 [12]
cy7c056v cy7c057v document #: 38-06055 rev. *f page 10 of 27 switching characteristics over the operating range [13] parameter description cy7c056v cy7c057v unit -12 -15 min max min max read cycle t rc read cycle time 12 ? 15 ? ns t aa address to data valid ? 12 ? 15 ns t oha output hold from address change 3 ? 3 ? ns t ace [14, 15] ce low to data valid ? 12 ? 15 ns t doe oe low to data valid ? 8 ? 10 ns t lzoe [14, 16, 17, 18] oe low to low z 0 ? 0 ? ns t hzoe [14, 16, 17, 18] oe high to high z ? 10 ? 10 ns t lzce [14, 13, 17, 18] ce low to low z 3 ? 3 ? ns t hzce [14, 16, 17, 18] ce high to high z ? 10 ? 10 ns t lzbe byte enable to low z 3 ? 3 ? ns t hzbe byte enable to high z ? 10 ? 10 ns t pu [14, 18] ce low to power-up 0 ? 0 ? ns t pd [14, 18] ce high to power-down ? 12 ? 15 ns t abe [15] byte enable access time ? 12 ? 15 ns write cycle t wc write cycle time 12 ? 15 ? ns t sce [14, 15] ce low to write end 10 ? 12 ? ns t aw address valid to write end 10 ? 12 ? ns t ha address hold from write end 0 ? 0 ? ns t sa [15] address set-up to write start 0 ? 0 ? ns t pwe write pulse width 10 ? 12 ? ns t sd data set-up to write end 10 ? 10 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe [17, 18] r/w low to high z ? 10 ? ? ns t lzwe [17, 18] r/w high to low z 3 ? 3 ? ns t wdd [19] write pulse to data delay ? 25 ? ? ns t ddd [19] write data valid to read data valid ? 20 ? 25 ns busy timing [20] t bla busy low from address match ? 12 ? 15 ns t bha busy high from address mismatch ? 12 ? 15 ns t blc busy low from ce low ? 12 ? 15 ns notes 13. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3.0 v, and output loading of the specified i oi /i oh and 10-pf load capacitance. 14. ce is low when ce 0 ? v il and ce 1 ?? v ih 15. to access ram, ce = l and sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 16. at any given temperature and voltag e condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 17. test conditions used are load 2. 18. this parameter is guaranteed by design, but it is not production tested. for information on port-to-port delay through ram c ells from writing port to reading port, refer to read timing with busy waveform. 19. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wa veform. 20. test conditions used are load 1.
cy7c056v cy7c057v document #: 38-06055 rev. *f page 11 of 27 data retention mode the cy7c056v and cy7c057v are designed with battery backup in mind. data retention voltage and supply current are guaranteed over temp erature. the following rules ensure data retention: 1. chip enable (ce ) [23] must be held high during data retention, within v dd to v dd ? 0.2 v. 2. ce must be kept between v dd ? 0.2 v and 70% of v dd during the power-up and power-down transitions. 3. the ram can begin operation >t rc after v dd reaches the minimum operating voltage (3.15 volts). notes 21. test conditions used are load 1. 22. t bdd is a calculated parameter and is the greater of t wdd ?t pwe (actual) or t ddd ?t sd (actual). 23. ce is low when ce 0 ? v il and ce 1 ?? v ih . 24. ce = v dd , v in = v ss to v dd , t a = 25 ? c. this parameter is guaranteed but not tested. busy timing [21] t bhc busy high from ce high ? 12 ? 15 ns t ps port set-up for priority 5 ? 5 ? ns t wb r/w low after busy (slave) 0 ? 0 ? ns t wh r/w high after busy high (slave) 11 ? 13 ? ns t bdd [22] busy high to data valid ? 12 ? 15 ns interrupt timing [21] ? t ins int set time ? 12 ? 15 ns t inr int reset time ? 12 ? 15 ns semaphore timing t sop sem flag update pulse (oe or sem )10? 10 ? ns t swrd sem flag write to read time 5 ? 5 ? ns t sps sem flag contention window 5 ? 5 ? ns t saa sem address access time ? 12 ? 15 ns switching characteristics over the operating range [13] (continued) parameter description cy7c056v cy7c057v unit -12 -15 min max min max timing parameter test conditions [24] max unit icc dr1 @ vdd dr = 2 v 50 ? a data retention mode 3.15 v 3.15 v v cc ? ? 2.0 v v cc to v cc ? 0.2 v v cc ce t rc v ih
cy7c056v cy7c057v document #: 38-06055 rev. *f page 12 of 27 switching waveforms notes 25. r/w is high for read cycles. 26. device is continuously selected. ce 0 = v il , ce 1 =v ih , and b 0 , b 1 , b 2 , b 3 , wa, ba are valid. this waveform cannot be used for semaphore reads. 27. oe = v il . 28. address valid prior to or coinciding with ce 0 transition low and ce 1 transition high. 29. to access ram, ce 0 = v il , ce 1 =v ih , b 0 , b 1 , b 2 , b 3 , wa, ba are valid, and sem = v ih . to access semaphore, ce 0 = v ih , ce 1 =v il and sem = v il or ce 0 and sem =v il , and ce 1 = b 0 = b 1 = b 2 = b 3 , =v ih . t rc t aa t oha data valid previous data valid data out address t oha read cycle no. 1 (either port address access) [25, 26, 27] t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out b 2 , b 3 , wa, ba ce 0 , ce 1 , b 0 , b 1 , current read cycle no. 2 (either port ce /oe access) [25, 28, 29] select valid oe data out t rc address t aa t oha ce 0 , ce 1 t lzce t abe t hzce t hzce t ace t lzce read cycle no. 3 (either port) [25, 27, 28, 29] b 0 , b 1 , b 2 , b 3 , wa, ba byte select valid chip select valid
cy7c056v cy7c057v document #: 38-06055 rev. *f page 13 of 27 notes 30. r/w must be high during all address transitions. 31. a write occurs during the overlap (t sce or t pwe ) of ce 0 =v il and ce 1 =v ih or sem =v il and b 0?3 low. 32. t ha is measured from the earlier of ce 0 /ce 1 or r/w or (sem or r/w ) going high at the end of write cycle. 33. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 34. to access ram, ce 0 = v il , ce 1 =sem = v ih . 35. to access byte b 0 , ce 0 = v il , b 0 = v il , ce 1 =sem = v ih . to access byte b 1 , ce 0 = v il , b 1 = v il , ce 1 =sem = v ih . to access byte b 2 , ce 0 = v il , b 2 = v il , ce 1 =sem = v ih . to access byte b 3 , ce 0 = v il , b 3 = v il , ce 1 =sem = v ih . 36. transition is measured 150 mv from steady state with a 5-pf l oad (including scope and jig). this parameter is sampled and n ot 100% tested. 37. during this period, the i/o pins are in the out put state, and input signals must not be applied. 38. if the ce 0 low and ce 1 high or sem low transition occurs simult aneously with or after the r/w low transition, the outputs remain in the high-impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce 0 , ce 1 r/w oe data out data in address t hzoe t sa t hzwe t lzwe write cycle no. 1: r/w controlled timing [30, 31, 32, 33] [36] [36] [33] [34, 35] note 37 note 37 chip select valid t aw t wc t sce t hd t sd t ha r/w data in address t sa write cycle no. 2: ce controlled timing [30, 31, 32, 38] ce 0 , ce 1 [34, 35] chip select valid
cy7c056v cy7c057v document #: 38-06055 rev. *f page 14 of 27 notes 39. ce 0 = high and ce 1 = low for the duration of the above timing (both write and read cycle). 40. i/o 0r = i/o 0l = low (request semaphore); ce 0r = ce 0l = high and ce 1r = ce 1l =low. 41. semaphores are reset (available to both ports) at cycle start. 42. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpr edictable. switching waveforms (continued) t sop t saa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ?a 2 semaphore read after write timing, either side [39] match t sps match r/w l sem l r/w r sem r timing diagram of semaphore contention [40, 41, 42] a 0l ?a 2l a 0r ?a 2r
cy7c056v cy7c057v document #: 38-06055 rev. *f page 15 of 27 note 43. ce 0l = ce 0r = low; ce 1l = ce 1r = high. switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l timing diagram of writ e with busy (m/s = high) [43] t pwe r/w busy t wb t wh write timing with busy input (m/s = low)
cy7c056v cy7c057v document #: 38-06055 rev. *f page 16 of 27 note 44. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side busy will be asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l,r busy r ce 0l , ce 1l ce 0r , ce 1r busy l address l,r busy timing diagram no. 1 (ce arbitration) [44] chip select valid chip select valid ce 0l , ce 1l ce 0r , ce 1r chip select valid chip select valid ce l valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l bus r t rc or t wc t bla t bha address r right address valid first: busy timing diagram no. 2 (address arbitration) [44] left address valid first:
cy7c056v cy7c057v document #: 38-06055 rev. *f page 17 of 27 notes 45. t ha depends on which enable pin (ce 0l /ce 1l or r/w l ) is deasserted first. 46. t ins or t inr depends on which enable pin (ce 0l /ce 1l or r/w l ) is asserted last. switching waveforms (continued) interrupt timing diagrams write 3fff (7fff for cy7c057v) t wc t ha read 3fff t rc t inr write 3ffe (7ffe for cy7c057v) t wc right side sets int l : left side sets int r : left side clears int l : read 3ffe t inr t rc address l r/w l int l oe l address r r/w r int r address r r/w r int r oe r address l r/w l int r t ins t ha t ins (7fff for cy7c057v) (7ffe for cy7c057v) [45] [46] [46] [46] [45] [46] ce 0l , ce 1l ce 0r , ce 1r ce 0r , ce 1r ce 0l , ce 1l chip select valid chip select valid chip select valid chip select valid right side clears int r :
cy7c056v cy7c057v document #: 38-06055 rev. *f page 18 of 27 architecture the cy7c056v and cy7c057v consist of an array of 16k and 32k words of 36 bits each of dual-port ram cells, i/o and address lines, and control signals (ce 0 /ce 1 , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared reso urces. with the m/s pin, the devices can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power-down feature controlled by ce 0 /ce 1 . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a vali d write. a writ e operation is controlled by either the r/w pin (see write cycle no. 1 waveform) or the ce 0 and ce 1 pins (see write cycle no. 2 waveform). required inputs for non-contention operations are summarized in ta b l e 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce [3] pins. data will be available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce [3] pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (3fff for the cy7c056v, 7fff for the cy7c057v) is the mailbox for the right port and the second-highest memory location (3ffe for the cy7c056v, 7ffe for the cy7c057v) is the mailbox for the left port. when one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other po rt?s mailbox without resetting the interrupt. the active state of th e busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin.the operation of the interrupts and their interaction with busy are summarized in ta b l e 2 . busy the cy7c056v and cy7c057v provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports? chip enables are asserted and an address match occurs within t ps of each other, the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided in order to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a write cycle during a contention situation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c056v and cy7c057v provide eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifi es its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value will be available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a 0), it assumes control of the shared resource, otherwise (reads a 1) it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a 1), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches. for normal semaphore access, ce [3] must remain high during sem low. a ce active semaphore access is also available. the semaphore may be accessed through the right port with ce 0r /ce 1r active by asserting the bus match select (bm) pin low and asserting the bus size select (size) pin high. the semaphore may be accessed through the left port with ce 0l /ce 1l active by asserting all b 0?3 byte select pins high. a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a norma l memory access. when writing or reading a semaphore, the other address pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a 1 will appear at the same semaphore address on the right port. that semaphore can now only be modified by the port showing 0 (the left port in this case). if the le ft port now relinquishes control by writing a 1 to the semaphore, the semaphore will be set to 1 for both ports. however, if the right port had requested the semaphore (written a 0) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. ta b l e 3 shows sample semaphore operations.
cy7c056v cy7c057v document #: 38-06055 rev. *f page 19 of 27 table 1. non-contending read/write [47] inputs outputs ce r/w oe b 0 , b 1 , b 2 , b 3 sem i/o 0 ? i/o 35 operation h x x x h high z deselected: power-down x x x all h h high z deselected: power-down l l x h/l h data in and high z write to selected bytes only l l x all l h data in write to all bytes l h l h/l h data out and high z read selected bytes only l h l all l h data out read all bytes x x h x x high z outputs disabled h h l x l data out read data in semaphore flag x h l all h l data out read data in semaphore flag h x x l data in write d in0 into semaphore flag x x all h l data in write d in0 into semaphore flag l x x any l l not allowed table 2. interrupt operation example (assumes busy l = busy r = high) [47, 48] left port right port function r/w l ce l oe l a 0l?13l int l r/w r ce r oe r a 0r?13r int r set right int r flag l l x 3fff x x x x x l [50] reset right int r flag x x x x x x l l 3fff h [49] set left int l flag x x x x l [49] l l x 3ffe x reset left int l flag x l l 3ffe h [50] x x x x x table 3. semaphore operation example function i/o 0 ? i/o 8 left i/o 0 ? i/o 8 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free notes 47. ce is low when ce 0 ? v il and ce 1 ?? v ih . 48. a 0l?14l and a 0r?14r , 7fff/7ffe for the cy7c057v. 49. if busy r =l, then no change. 50. if busy l =l, then no change.
cy7c056v cy7c057v document #: 38-06055 rev. *f page 20 of 27 when reading a semaphore, data lines 0 through 8 output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. when reading a semaphore, data lines 0 through 8 output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. when reading a semaphore, data lines 0 through 8 output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. bus match operation the right port of the cy7c057 v 32kx36 dual-port sram can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data i/o. the data lines are divided into four lanes, each consisting of 9 bits (byte-size data lines). the bus match select (bm) pin wor ks with bus size select (size) to select bus width (long-word, word, or byte) for the right port of the dual-port device. the data sequencing arrangement is selected using the word address (wa) and byte address (ba) input pins. a logic ?0? applied to both the bus match select (bm) notes 51. bm and size must be configured one clock cycle be fore operation is guaranteed. 52. in x36 mode wa and ba pins are ?don?t care.? 53. in x18 mode ba pin is a ?don?t care.? 54. dq represents data output of the chip. right port configuration [51, 52, 53] bm size configuration i/o pins used 0 0 x36 (standard) i/o 0?35 0 1 x36 (ce active sem mode) i/o 0?35 1 0 x18 i/o 0?17 1 1 x9 i/o 0?8 right port operation configuration wa ba data accessed [54] i/o pins used x36 x x dq 0?35 i/o 0?35 x18 0 x dq 0?17 i/o 0?17 x18 1 x dq 18?35 i/o 0?17 x9 0 0 dq 0?8 i/o 0?8 x9 0 1 dq 9?17 i/o 0?8 x9 1 0 dq 18?26 i/o 0?8 x9 1 1 dq 27?35 i/o 0?8 left port operation control pin effect b0 i/o 0?8 byte control b1 i/o 9?17 byte control b2 i/o 18?26 byte control b3 i/o 27?35 byte control 9 / ba wa cy7c056v cy7c057v 16k/32kx36 dual port bm size 9 / 9 / 9 / x9, x18, x36 / bus mode x36 /
cy7c056v cy7c057v document #: 38-06055 rev. *f page 21 of 27 pin and to the bus size select (size) pin will select long-word (36-bit) operation. a logic ?1? level applied to the bus match select (bm) pin will enable either byte or word bus width operation on the right port i/os depending on the logic level applied to the size pin. the level of bus match select (bm) must be static throughout device operation. normally, the bus size select (size) pin would have no standard-cycle application when bm = low and the device is in long-word (36-bit) operation. a ?special? mode has been added however to disable all right port i/os while the chip is active. this i/o disable mode is implemented when size is forced to a logic ?1? while bm is at a logic ?0?. it allows the bus-matched port to support a chip enable ?don?t care? semaphore read/write access similar to that provided on the left port of the device when all byte select (b 0?3 ) control inputs are deselected. the bus size select (size) pin selects either a byte or word data arrangement on the right port when the bus match select (bm) pin is high. a logic ?1? on the size pin when the bm pin is high selects a byte bus (9-b it) data arrangement) . a logic ?0? on the size pin when the bm pin is high selects a word bus (18-bit) data arrangement. the level of the bus size select (size) must also be static throughout normal device operation. long-word (36-bit) operation bus match select (bm) and bus size select (size) set to a logic ?0? will enable standard cycle long-word (36-bit) operation. in this mode, the right port?s i/o operat es essentially in an identical fashion as does the left port of the dual-port sram. however no byte select control is available. all 36 bits of the long-word are shifted into and out of the right port?s i/o buffer stages. all read and write timing parameters may be identical with respect to the two data ports. when the right port is configured for a long-word size, word address (wa), and byte address (ba) pins have no application and their inputs are ?don?t care? [55] for the external user. word (18-bit) operation word (18-bit) bus sizing operation is enabled when bus match select (bm) is set to a logic ?1? and the bus sze select (size) pin is set to a logic ?0.? in this mode, 18 bits of data are ported through i/o 0r?17r . the level applied to the word address (wa) pin during word bus size operation determines whether the most-significant or least-signif icant data bits are ported through the i/o 0r?17r pins in an upper word/lower word select fashion (note that when the right port is configured for word size operation, the byte address pin has no application and its input is ?don?t care? [55] ). device operation is accomplishe d by treating the wa pin as an additional address input and using standard cycle address and data setup/hold times. when transferring data in word (18-bit) bus match format, the unused i/o 18r?35r pins are three-stated. byte (9-bit) operation byte (9-bit) bus sizing operation is enabled when bus match select (bm) is set to a logic ?1? an d the bus size select (size) pin is set to a logic ?1.? in this mode, data is ported through i/o 0r?8r in four groups of 9-bit bytes. a particular 9-bit byte group is selected according to the levels applied to the word address (wa) and byte address (ba) input pins. device operation is accomplished by treating the word address (wa) pin and the byte address (ba) pins as additional address inputs having standard cycle address and data set-up/hold times. when transferring data in byte (9-bit) bus match format, the unused i/o 9r?35r pins are three-stated. note 55. even though a logic level applied to a ?don?t care? input will not change the logical operation of the dual-port, inputs tha t are temporarily a ?don?t care? (along with unused inputs) must not be allowed to float. they must be forced either high or low. i/os rank wa ba i/o 27r?35r upper-msb 1 1 i/o 18r?26r lower-msb 1 0 i/o 9r?17r upper-msb 0 1 i/o 0r?8r lower-msb 0 0
cy7c056v cy7c057v document #: 38-06055 rev. *f page 22 of 27 ordering information 16k x 36 3.3 v asynchronous dual port sram 32k x 36 3.3 v asynchronous dual port sram ordering code definition speed (ns) ordering code package name package type operating range 15 cy7c056v-15axc a144 144-pin pb-free thin quad flat pack commercial speed (ns) ordering code package name package type operating range 12 CY7C057V-12AXC a144 144-pin pb-free thin quad flat pack commercial 15 cy7c057v-15axc a144 144-pin pb-free thin quad flat pack commercial cy7c057v-15axi a144 144-pin pb-free thin quad flat pack industrial cy7c057v-15bbi bb172 172-ball ball grid array (bga) industrial cy7c057v-15bbxc bb172 172-ball ball grid array (bga) cy 7c x xx company id: cy = cypress 7c = dual port sram width: 05=x36 operating range c = commercial i = industrial x depth: 6=16k or 7=32k xx x package: a=tqfp or bb=fbga 0 speed grade : 12ns/15ns x x : pb free (rohs compliant) x x = v: 3.3 v
cy7c056v cy7c057v document #: 38-06055 rev. *f page 23 of 27 package diagrams figure 3. 144-pin plastic thin quad flat pack (tqfp) a144 51-85047 *d
cy7c056v cy7c057v document #: 38-06055 rev. *f page 24 of 27 package diagrams (continued) figure 4. 172-ball fbga (15 x 15 x 1.25 mm) bb172 51-85114 *d
cy7c056v cy7c057v document #: 38-06055 rev. *f page 25 of 27 acronyms document conventions units of measure acronym description bga ball grid array cmos complementary metal oxide semiconductor i/o input/output sram static random access memory tqfp thin quad plastic flatpack symbol unit of measure c degree celsius mhz mega hertz a microamperes ma milliamperes mv millivolts ns nanoseconds ? ohms pf picofarad vvolts wwatts
cy7c056v cy7c057v document #: 38-06055 rev. *f page 26 of 27 document history page document title: cy7c056v/cy7c057v 3.3 v 16k/32k x 36 flex36? asynchronous dual-port static ram document number: 38-06055 rev. ecn no. issue date orig. of change description of change ** 110214 12/16/01 szv change from sp ec number: 38-00742 to 38-06055 *a 122305 12/27/02 rbi power up requirements added to maximum ratings information *b 393770 see ecn yim added pb-free logo added pb-free parts to ordering information: cy7c056v-12axc, cy7c056v-15axc, CY7C057V-12AXC, cy7c057v-15axc, cy7co57v-15axi *c 2897217 03/22/2010 rame updated ordering information updated package diagrams *d 3093365 11/25/2010 admu removed part cy7c057v-15bbc added part cy7c057v-15axi updated datasheet as per new template added acronyms and units of measure table added ordering code definition updated all footnotes. *e 3210221 03/30/2011 admu removed parts cy7c056v-15ac and cy7c057v-12bbc from the ordering information table. *f 3403652 10/14/2011 admu removed cy7c057v-12ac from ordering information updated package diagrams .
document #: 38-06055 rev. *f revised october 14, 2011 page 27 of 27 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c056v cy7c057v ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 flex36 is a trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be th e trademarks of their respective holders.

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